FPGA design of the fast decoder for burst errors correction; Journal of Physics: Conference Series; Vol. 803 : Information Technologies in Business and Industry (ITBI2016)

FPGA design of the fast decoder for burst errors correction; Journal of Physics: Conference Series; Vol. 803 : Information Technologies in Business and Industry (ITBI2016)

Bibliographic Details
Parent link:Journal of Physics: Conference Series
Vol. 803 : Information Technologies in Business and Industry (ITBI2016).— 2017.— [012105, 6 p.]
Corporate Author: Национальный исследовательский Томский политехнический университет (ТПУ) Институт кибернетики (ИК)
Other Authors: Mytsko E. A. Evgeniy Aleksandrovich, Malchukov A. N. Andrey Nikolaevich, Zoev I. V. Ivan Vladimirovich, Ryzhova S. E. Svetlana Evgenievna, Kim V. L. Valery Lvovich
Summary:Title screen
The paper is about FPGA design of the fast single stage decoder for correcting burst errors during data transmission. The decoder allows correcting burst errors with 3 bits for a 15 bit codeword and a 7 bit check unit. The description of a generator polynomial search algorithm for building error-correcting codes was represented. The module structure of the decoder was designed for FPGA implementation. There are modules, such as remainder, check_pattern, decoder2, implemented by asynchronous combinational circuits without memory elements, and they process each codeword shift in parallel. Proposed implementation allows getting high performance about ~20 ns.
Language:English
Published: 2017
Subjects:
электронный ресурс
труды учёных ТПУ
дизайн
декодеры
коррекция
ошибки
передача данных
полиномы
ПЛИС
производительность
Online Access:http://dx.doi.org/10.1088/1742-6596/803/1/012105
http://earchive.tpu.ru/handle/11683/38166
Format: Electronic Book Chapter
KOHA link:https://koha.lib.tpu.ru/cgi-bin/koha/opac-detail.pl?biblionumber=654377

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