FPGA design of the fast decoder for burst errors correction
| Parent link: | Journal of Physics: Conference Series Vol. 803 : Information Technologies in Business and Industry (ITBI2016).— 2017.— [012105, 6 p.] |
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| Other Authors: | , , , , |
| Summary: | Title screen The paper is about FPGA design of the fast single stage decoder for correcting burst errors during data transmission. The decoder allows correcting burst errors with 3 bits for a 15 bit codeword and a 7 bit check unit. The description of a generator polynomial search algorithm for building error-correcting codes was represented. The module structure of the decoder was designed for FPGA implementation. There are modules, such as remainder, check_pattern, decoder2, implemented by asynchronous combinational circuits without memory elements, and they process each codeword shift in parallel. Proposed implementation allows getting high performance about ~20 ns. |
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2017
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| Online Access: | http://dx.doi.org/10.1088/1742-6596/803/1/012105 http://earchive.tpu.ru/handle/11683/38166 |
| Format: | Electronic Book Chapter |
| KOHA link: | https://koha.lib.tpu.ru/cgi-bin/koha/opac-detail.pl?biblionumber=654377 |