FPGA design of the fast decoder for burst errors correction; Journal of Physics: Conference Series; Vol. 803 : Information Technologies in Business and Industry (ITBI2016)
| Parent link: | Journal of Physics: Conference Series Vol. 803 : Information Technologies in Business and Industry (ITBI2016).— 2017.— [012105, 6 p.] |
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| Ente Autore: | |
| Altri autori: | , , , , |
| Riassunto: | Title screen The paper is about FPGA design of the fast single stage decoder for correcting burst errors during data transmission. The decoder allows correcting burst errors with 3 bits for a 15 bit codeword and a 7 bit check unit. The description of a generator polynomial search algorithm for building error-correcting codes was represented. The module structure of the decoder was designed for FPGA implementation. There are modules, such as remainder, check_pattern, decoder2, implemented by asynchronous combinational circuits without memory elements, and they process each codeword shift in parallel. Proposed implementation allows getting high performance about ~20 ns. |
| Lingua: | inglese |
| Pubblicazione: |
2017
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| Soggetti: | |
| Accesso online: | http://dx.doi.org/10.1088/1742-6596/803/1/012105 http://earchive.tpu.ru/handle/11683/38166 |
| Natura: | MixedMaterials Elettronico Capitolo di libro |
| KOHA link: | https://koha.lib.tpu.ru/cgi-bin/koha/opac-detail.pl?biblionumber=654377 |
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| 200 | 1 | |a FPGA design of the fast decoder for burst errors correction |f E. A. Mytsko [et al.] | |
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| 320 | |a [References: 20 tit.] | ||
| 330 | |a The paper is about FPGA design of the fast single stage decoder for correcting burst errors during data transmission. The decoder allows correcting burst errors with 3 bits for a 15 bit codeword and a 7 bit check unit. The description of a generator polynomial search algorithm for building error-correcting codes was represented. The module structure of the decoder was designed for FPGA implementation. There are modules, such as remainder, check_pattern, decoder2, implemented by asynchronous combinational circuits without memory elements, and they process each codeword shift in parallel. Proposed implementation allows getting high performance about ~20 ns. | ||
| 461 | 0 | |0 (RuTPU)RU\TPU\network\3526 |t Journal of Physics: Conference Series | |
| 463 | 0 | |0 (RuTPU)RU\TPU\network\19875 |t Vol. 803 : Information Technologies in Business and Industry (ITBI2016) |o International Conference, 21–26 September 2016, Tomsk, Russian Federation |o [proceedings] |f National Research Tomsk Polytechnic University (TPU) ; eds. N. V. Martyushev ; V. S. Avramchuk ; V. A. Faerman |v [012105, 6 p.] |d 2017 | |
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| 701 | 1 | |a Malchukov |b A. N. |c specialist in the field of informatics and computer technology |c Associate Professor of Tomsk Polytechnic University, Candidate of technical sciences |f 1982- |g Andrey Nikolaevich |3 (RuTPU)RU\TPU\pers\32409 |9 16360 | |
| 701 | 1 | |a Zoev |b I. V. |c Specialist in the field of informatics and computer technology |c Programmer of Tomsk Polytechnic University |f 1993- |g Ivan Vladimirovich |3 (RuTPU)RU\TPU\pers\38250 | |
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