Finding False Paths in Sequential Circuits

Finding False Paths in Sequential Circuits

Bibliografiset tiedot
Parent link:Russian Physics Journal
Vol. 60, iss. 10.— 2018.— [P. 1837-1844]
Yhteisötekijä: Национальный исследовательский Томский политехнический университет Школа базовой инженерной подготовки Отделение математики и информатики
Muut tekijät: Matrosova A. Yu. Anzhela Yurjevn, Andreeva V. V. Valentina Valerjevna, Chernyshov S. V. Semen Vladimirovich, Rozhkova S. V. Svetlana Vladimirovna, Kudin D. V. Dmitry Valerjevich
Yhteenveto:Title screen
Method of finding false paths in sequential circuits is developed. In contrast with heuristic approaches currently used abroad, the precise method based on applying operations on Reduced Ordered Binary Decision Diagrams (ROBDDs) extracted from the combinational part of a sequential controlling logic circuit is suggested. The method allows finding false paths when transfer sequence length is not more than the given value and obviates the necessity of investigation of combinational circuit equivalents of the given lengths. The possibilities of using of the developed method for more complicated circuits are discussed.
Режим доступа: по договору с организацией-держателем ресурса
Kieli:englanti
Julkaistu: 2018
Aiheet:
электронный ресурс
труды учёных ТПУ
sequential circuit
reduced ordered binary decision diagram (ROBDD)
false path
equivalent normal form
path delay fault
Linkit:https://doi.org/10.1007/s11182-018-1290-0
Aineistotyyppi: Elektroninen Kirjan osa
KOHA link:https://koha.lib.tpu.ru/cgi-bin/koha/opac-detail.pl?biblionumber=667246
Kuvaus
Yhteenveto:Title screen
Method of finding false paths in sequential circuits is developed. In contrast with heuristic approaches currently used abroad, the precise method based on applying operations on Reduced Ordered Binary Decision Diagrams (ROBDDs) extracted from the combinational part of a sequential controlling logic circuit is suggested. The method allows finding false paths when transfer sequence length is not more than the given value and obviates the necessity of investigation of combinational circuit equivalents of the given lengths. The possibilities of using of the developed method for more complicated circuits are discussed.
Режим доступа: по договору с организацией-держателем ресурса
DOI:10.1007/s11182-018-1290-0

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