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| LEADER |
00000nam0a2200000 4500 |
| 001 |
151771 |
| 005 |
20231101221602.0 |
| 010 |
|
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|a 9780387364957
|
| 035 |
|
|
|a (RuTPU)RU\TPU\book\164547
|
| 090 |
|
|
|a 151771
|
| 100 |
|
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|a 20090127d2006 k y0engy50 ba
|
| 101 |
0 |
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|a eng
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| 102 |
|
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|a US
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| 105 |
|
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|a a z 001zy
|
| 200 |
1 |
|
|a SystemVerilog For Design. A Guide to Using System Verilog for Hardware Design and Modeling
|f S. Sutherland, S. Davidmann, P. Flake
|
| 205 |
|
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|a Second Edition
|
| 210 |
|
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|a New York
|c Springer
|d 2006
|
| 215 |
|
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|a 418 p.
|c il.
|
| 320 |
|
|
|a Index: p. 415-418.
|
| 606 |
1 |
|
|a Дизайн
|x Промышленные предприятия
|2 stltpush
|3 (RuTPU)RU\TPU\subj\9467
|9 36711
|
| 610 |
1 |
|
|a проектирование
|
| 610 |
1 |
|
|a моделирование
|
| 610 |
1 |
|
|a информационные технологии
|
| 610 |
1 |
|
|a SystemVerilog
|
| 610 |
1 |
|
|a английский язык
|
| 675 |
|
|
|a 658.512.26
|v 3
|
| 700 |
|
1 |
|a Sutherland
|b S.
|g Stuart
|
| 701 |
|
1 |
|a Davidmann
|b S.
|g Simon
|
| 701 |
|
1 |
|a Flake
|b P.
|g Peter
|
| 801 |
|
1 |
|a RU
|b 63413507
|c 20090127
|g PSBO
|
| 801 |
|
2 |
|a RU
|b 63413507
|c 20090310
|g PSBO
|
| 942 |
|
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|c BK
|
